Modern logic designs often employ multiple clock domains to support high-speed communication where synchronous transfers using a single board clock would not be practical. One example of this application can be seen in source synchronous communication where a clock or strobe is sent along with the data. Another example relates to recovered clocks where the information needed to re-construct the clock is embedded in the data stream.
Having a number of isolated clock domains is generally not useful in a logic design. Data needs to flow between the clock domains. In order to transfer data between clocks that are asynchronous to one another, synchronizers are needed to synchronize asynchronous data to a given clock. For every clock cycle, a synchronizer makes a decision whether a given signal is a 0 or 1.
FIG. 1 illustrates an exemplary synchronizer 100. The synchronizer 100 includes 3 registers connected in series. The series of registers is used because each register has a certain probability of going metastable. A register experiences metastability when data changes when the register is sampling and the register goes into an intermediate state. The register will eventually decide whether it should output a 0 or a 1, but the length of time it takes to decide is a super-linear function of how close the data arrives to the clock. If the time it takes to make a decision is so long that the next register in the chain cannot sample a clean signal, that subsequent register can also go metastable. If this indecision makes it through the synchronizer chain, the logic circuit may start to fail by behaving incorrectly. Different parts of the design could interpret the signal differently.
The mean-time-between-failure (MTBF) where all the stages of a synchronizer chain fail to decide in time is a parameter given to assess the quality of a synchronizer. The MTBF can be computed with the following relationship.MTBF=[e^[(chain slack)/c2]]/(fclk*fdata*c1)
In this relationship, fclk is the frequency of the sampling clock, fdata is the incoming data rate, c1 is the window of the time around a clock edge where a data transition will cause metastability, and c2 is the time constant of resolution. Chain slack is the total slack of all the hops of the chain and it is the amount of time the chain has to resolve metastability. The more time (slack) available, the larger the MTBF will be. Also, the smaller the time constant of resolution, the larger the MTBF will be.
Synchronization is also important for sampling the physical world. Synchronizing the physical world is typically less prone to failure because the data rates are generally much smaller than in high-speed communication, and the MTBF is inversely proportional to data rate.
In the past, designers would build synchronizers of a pre-determined length that statistically seemed reasonable enough to guarantee good system MTBFs regardless of the synthesis, placement, and routing of the synchronizer. The designers would also often be required to explicitly mark these registers to prevent them from being re-timed or duplicated. The designers also had to manually inspect the final implementation of the synchronizers.